In the case of UCP (Uniform Channel Program) flash memories, two bit lines are necessary for the connection of source and drain of the memory transistors. As a result, the pitch dimension in the cell array in the direction perpendicular to the bit lines cannot become smaller than twice the minimum pitch between the metal interconnects. Routing the bit lines in different wiring planes also does not change anything about this, in principle, since the distance between the interconnects and the contact holes (vias) for connecting different wiring planes quite generally has essentially the same magnitude as the distance between two interconnects.
In the direction parallel to the bit lines, the pitch dimension is generally already configured in minimal fashion corresponding to the state of the art. The present-day concepts for UCP memories, therefore, use particularly aggressive metal design rules in order to enable cell sizes that are as small as possible. A competitive disadvantage nevertheless remains in comparison with other concepts, particularly in the case of large and very large memories.
A substantial reduction of the cell size can only be achieved if it is possible to bury one of the two bit lines, i.e., to route it essentially beneath the substrate surface. Such a buried bit line has to satisfy further requirements with regard to its resistance and capacitance per unit length and must not substantially increase the production costs. Moreover, the conductive material used for the buried bit line has to withstand the temperature budget of the subsequent processes without any damage.